The present invention relates generally to data transfer on a communications bus. More particularly, the present invention relates to a mechanism for strobe phase tracking during a master changeover on the communication bus.
A multiprocessor system increases system performance because multiple processors operate in parallel. A typical multiprocessor system has a number of processors attached to a communication bus. Although each processor can only use the bus one at a time, bus protocols has been developed to optimize the bus utilization.
In such a multiprocessor system, one part of the communication bus, the data bus, is one of the most important resources because all of the information exchanges take place on this bus. It is therefore important that the data bus is efficiently utilized. In the multiprocessor system the data is transferred from processor to processor in accordance with a predefined clocking scheme. A system bus clock typically clocks data out of a sending processor and into a receiving processor. Consequently, it takes one complete clock cycle of a system bus clock to transfer data from one processor to another processor. Data can be transferred in a source synchronous fashion in order to increase the speed of the data transmission. In source synchronous transmission, the data transfer is typically clocked by two differential strobe signals which are phase shifted such that the active edges as provided by both strobes correspond to a fast transfer clock which is typically shorter than the period of the system bus clock. These strobes are used by the receiving processor to latch the data.
Differential strobe signals mean that both active low and active high strobes are used. This introduces complexity in an active low bus by requiring that one of the strobes be pre and post driven from and to a steady state logic 1 value. Furthermore, the pre and post driving of the strobes need to be taken into consideration at the receiving processors to ensure proper data capture and to decide which strobe needs to be pre driven during a next data transfer. The main problem associated with this differential multiprocessor approach is continuous data transfers with changes in the bus ownership, i.e., when another processor becomes the sending processor or xe2x80x9cmasterxe2x80x9d and takes over the data bus.
Accordingly, there is a need in the technology to have a mechanism for strobe phase tracking to ensure proper strobe pre and post driving as well as accurately capturing data.
Embodiments of the present invention are directed to a method and apparatus for ensuring proper strobe pre and post driving between a first data transfer and a second data transfer in a computing system. The method includes generating a first strobe signal and a second strobe signal, pre-driving one of said first and second strobe signals before the first data transfer, determining which of said first and second strobe signals will be post driven, and pre-driving one of said first and second strobe signals before the second data transfer.